(1888PressRelease)
March 02, 2008 - Report Buyer, the online destination for business intelligence for major industry sectors, has added a new report showing that the improvements of chip density versus cost in the semi-conductor industry have created a substantial gap between the scaling of the chip front end and the packaging assembly at the back end.
According to “WLP & Embedded Die Technologies 2008” Wafer Level Packaging (WLP) is about to fill that gap by allowing the packaging and assembly steps to be performed at the wafer level.
The report shows that for CMOS imagers, WLP is already an industrial reality. Today, about 35% of CMOS imagers found in the latest cell-phone and notebook cameras are encapsulated in a WL-CSP. The report forecast that the technology could penetrate about 63% of this market by 2012 and should progressively spread from CIF/VGAs to higher resolution image sensors.
The report shows that as wafer sizes increase, the cost of packaging will decrease, even in the most stringent semiconductor applications.
As a generic description, WLP should be defined as “all packaging and assembly processes done at the wafer level, the last step being the chip dicing”. Subsequently, WLP does not require any intermediate substrate interposer: wafer level packaged components are directly “surface mountable” onto the circuit board. WLP represents a breakthrough technology to be implemented even in the most cost sensitive applications as it will scale favourably with the trend to manufacture on ever increasing wafer diameters.
The report will provide precise descriptions of the different types of devices using WLP and their related manufacturing challenges as well as market information.
“WLP & Embedded Die Technologies 2008” is available from Report Buyer.
Report Buyer product ID: YOL00060
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http://www.reportbuyer.com/computing_electronics/nanotechnology/nanostructured_materials.html
